View TNRLA024AE_9004024.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(c) 2014. renesas electronics corporation. all rights reserved. page 1 of 37 date: apr. 9 , 2014 renesas technical update 1753, shimonumabe, nakahara-ku, kawasaki-shi, kanagawa 211-8668 japan renesas electronics corporation product category mpu/mcu document no. tn-rl*-a024a/e rev. 1.00 title correction for incorrect description notice rl78/i1a descriptions in the hardware users manual rev. 2.10 changed information category technical notification applicable product rl78/i1a group r5f107xxx lot no. reference document rl78/i1a users manual: hardware rev. 2.10 r01uh0169ej0210 (jul. 2013) all lot this document describes misstatements found in the rl78 /i1a hardware users manual rev. 2.10 (r01uh0169ej0210). corrections correction item applicable page contents figure 7-19. format of peripheral function switch register 0 (pfsel0) p.303 incorrect descriptions revised figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) p.380, 381 incorrect descriptions revised figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) p.382, 383 incorrect descriptions revised figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) p.384,385 incorrect descriptions revised figure 14-1. block diagram of comparator p.527 incorrect descriptions revised figure 14-12. format of peripheral function switch register 0 (pfsel0) p.538 incorrect descriptions revised 14. 5 caution for using ti mer kb simultaneous operation function - caution added timing chart of snooze mode operation p. 666, 667, 669 incorrect descriptions revised table 20-1. interrupt source li st (2/3) p.898 caution added figure 20-1. basic configuration of interrupt function p.900 incorrect descriptions revised table 21-1. operating stat uses in halt mode (2/2) p.931 incorrect descriptions revised table 21-2. operating st atuses in stop mode p.936 incorrect descriptions revised table 21-3. operating statuses in snooze mode p.942 incorrect descriptions revised 32.7 data memory stop mode low supply voltage data retention characteristics p.1100 explanations added 33.7 data memory stop mode low supply voltage data retention characteristics p.1142 explanations added
renesas technical update tn-rl*-a024a/e date: ap r. 9 , 2014 page 2 of 37 document improvement the above corrections will be made for the next revision of the hardware users manual. corrections in the hardware users manual no. applicable item applicable page in this notice document no. english r01uh0169ej0210 1 figure 7-19. format of peripheral function switch register 0 (pfsel0) p.303 p.3 2 figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) p.380, 381 p.5 3 figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) p.382, 383 p.9 4 figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) p.384,385 p.13 5 figure 14-1. block diagram of comparator p.527 p.17 6 figure 14-12. format of peripheral function switch register 0 (pfsel0) p.538 p.19 7 14. 5 caution for using ti mer kb simultaneous operation function - p.21 8 timing chart of snooze mode o peration p.666, 667, 669 p.24 9 table 20-1. interrupt sour ce list (2/3) p.898 p.27 10 figure 20-1. basic configuration of interrupt function p.900 p.28 11 table 21-1. operating stat uses in halt mode (2/2) p.931 p.30 12 table 21-2. operating st atuses in stop mode p.936 p.32 13 table 21-3. operating statuses in snooze mode p.942 p.34 14 32.7 data memory stop mode low supply voltage data retention characteristics p.1100 p.35 15 33.7 data memory stop mode low supply voltage data retention characteristics p.1142 p.36 incorrect: bold with underline ; correct: gray hatched issued document history rl78/i1a incorrect description notice, issued document history document number issue date description tn-rl*-a024a/e apr . 9 , 2014 f irst edition issued incorrect descriptions of no.1 to no.15 revised (this notice)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 3 of 37 1. figure 7-19. format of peripheral function switch register 0 (pfsel0) incorrect descriptions of the tmrsten1 and tmrsten0 bits of peripheral function switch register 0 (pfsel0) are revised, and note is added. incorrect: figure 7-19. format of peripheral function switch register 0 (pfsel0) address: f05c6h after reset: 00h r/w symbol 7 <6> <5> <4> 3 2 <1> <0> pfsel0 0 cmp2sten cmp0sten pnfen adtrg11 adtrg10 tmrsten1 tmrsten0 cmp2sten cmp0sten compar ator interrupt selection see chapter 14 comparator . pnfen use/do not use external interrupt intp20 noise filter 0 use noise filter 1 do not use noise filter adtrg11 adtrg10 timer trigger selection for a/d conversion 0 0 timer kb0 trigger source 0 1 timer kb1 trigger source 1 0 timer kb2 trigger source 1 1 setting prohibited tmrsten1 function selection for external interrupt intp21 0 external interrupt function (external interrupt generation enabled, timer restart disabled) 1 timer restart function (external interrupt generation disabled, standby release disabled) tmrsten0 function selection for external interrupt intp20 0 external interrupt function (external interrupt generation enabled, timer restart disabled) 1 timer restart function (external interrupt generation disabled, standby release disabled) remark see figure 14-1 block diagram of comparator .
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 4 of 37 correct: figure 7-19. format of peripheral function switch register 0 (pfsel0) address: f05c6h after reset: 00h r/w symbol 7 <6> <5> <4> 3 2 <1> <0> pfsel0 0 cmp2sten cmp0sten pnfen adtrg11 adtrg10 tmrsten1 tmrsten0 cmp2sten cmp0sten compar ator interrupt selection see chapter 14 comparator . pnfen use/do not use external interrupt intp20 noise filter 0 use noise filter 1 do not use noise filter adtrg11 adtrg10 timer trigger selection for a/d conversion 0 0 timer kb0 trigger source 0 1 timer kb1 trigger source 1 0 timer kb2 trigger source 1 1 setting prohibited tmrsten1 switch of external interrupt intp21 note 0 external interrupt function is selected (st op mode release enabled, ti mer restart disabled). 1 timer restart function is selected (stop m ode release disabled, timer restart enabled). tmrsten0 switch of external interrupt intp20 note 0 external interrupt function is selected (st op mode release enabled, ti mer restart disabled). 1 timer restart function/forced output stop functi on 2 is selected (stop mode release disabled, timer restart enabled). note when intp20 or intp21 is used as a trigger of the ti mer kb forced output stop function 2 or timer restart function, see 14. 5 caution for using timer kb simultaneous operation function . remark see figure 14-1 block diagram of comparator .
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 5 of 37 2. figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) incorrect descriptions of forced output st op function control register 0p (tkbpactl0p) are revised, and note is added. incorrect: figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) (1/2) address: f0630h (tkbpactl00), f0632h (tkbpactl01) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 tkbpactl0p tkbpafxs0p3 tkbpafxs0p2 tkbpafxs0p1 tkbpafxs0p0 0 0 0 tkbpafcm0p 7 6 5 4 3 2 1 0 0 tkbpahzs0p2 tkbpahzs0p1 tkbpahzs0p0 tkbpa hcm0p1 tkbpahcm0p0 tkbpamd0p1 tkbpamd0p0 tkbpafxs0p3 external interruption trigger select ion for forced output stop function 2 0 intp20 can not be used as a trigger. 1 intp20 can be used as a trigger. tkbpafxs0p2 comparator trigger selection for forced output stop function 2 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. tkbpafxs0p1 comparator trigger selection for forced output stop function 2 0 comparator 1 can not be used as a trigger. 1 comparator 1 can be used as a trigger. tkbpafxs0p0 comparator trigger selection for forced output stop function 2 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. tkbpafcm0p operation mode selection for forced output stop function 2 0 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period. 1 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger.
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 6 of 37 figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) (2/2) tkbpahzs0p2 comparator trigger selection for forced output stop function 1 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. tkbpahzs0p1 comparator trigger selection for forced output stop function 1 0 comparator 1 can not be used as a trigger. 1 comparator 1 can be used as a trigger. tkbpahzs0p0 comparator trigger selection for forced output stop function 1 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. tkbpahcm0p1 tkbpahcm0p0 clear condition selection for forced output stop function 1 0 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when hi-z stop trigger (tkbpahtt0) = 1 is written, regardless of the trigger signal level. 0 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writing hi-z stop trigger (tkbpahtt0) = 1 is invalid. forced output stop function 1 is cleared when hi-z stop trigger (tkbpahtt0) = 1 is written while the trigger signal is in its inactive period. 1 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared at the next counter period after hi-z stop trigger (tkbpahtt0) = 1 is written, regardless of the trigger signal level. 1 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writing hi-z stop trigger (tkbpahtt0) = 1 is invalid. forced output stop function 1 is cleared at the next counter period after hi-z stop trigger (tkbpahtt0) = 1 is written when the trigger signal is in its inactive period. tkbpamd0p1 tkbpamd0p0 output status selection when executing forced output stop function forced output stop function 1 forced output stop function 2 0 0 hi-z output output fixed at low level 0 1 hi-z output output fixed at high level 1 0 output fixed at low level output fixed at low level 1 1 output fixed at high level output fixed at high level cautions 1. during timer operation, setting the other bits of the tkbpactl0p register is prohibited. however, the tkbpactl0p register can be refreshed (the same value is written). 2. be sure to clear bits 11 to 9 and 7 to ?0?. remark n = 0 to 2, p = 0, 1
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 7 of 37 correct: figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) (1/2) address: f0630h (tkbpactl00), f0632h (tkbpactl01) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 tkbpactl0p tkbpafxs0p3 tkbpafxs0p2 tkbpafxs0p1 tkbpafxs0p0 0 0 0 tkbpafcm0p 7 6 5 4 3 2 1 0 0 tkbpahzs0p2 tkbpahzs0p1 tkbpahzs0p0 tkbpa hcm0p1 tkbpahcm0p0 tkbpamd0p1 tkbpamd0p0 tkbpafxs0p3 external interruption trigger select ion for forced output stop function 2 0 intp20 can not be used as a trigger. 1 intp20 can be used as a trigger. note 1 tkbpafxs0p2 comparator trigger selection for forced output stop function 2 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. note 2 tkbpafxs0p1 comparator trigger selection for forced output stop function 2 0 comparator 1 can not be used as a trigger. 1 comparator 1 can be used as a trigger. note 3 tkbpafxs0p0 comparator trigger selection for forced output stop function 2 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. note 2 tkbpafcm0p operation mode selection for forced output stop function 2 0 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period. note 4 1 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger. note 4 tkbpahzs0p2 comparator trigger selection for forced output stop function 1 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. note 2 tkbpahzs0p1 comparator trigger selection for forced output stop function 1 0 comparator 1 can not be used as a trigger. 1 comparator 1 can be used as a trigger. note 3 tkbpahzs0p0 comparator trigger selection for forced output stop function 1 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. note 2
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 8 of 37 figure 7-73. format of forced output stop function control register 0p (tkbpactl0p) (2/2) tkbpahcm0p1 tkbpahcm0p0 clear condition selection for forced output stop function 1 0 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when forced out put stop function release trigger (tkbpahtt0p) = 1 is written, regard less of the trigger signal level. 0 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writ ing forced output stop function release trigger (tkbpahtt0p) = 1 is invalid. forced output stop function 1 is cleared when forced output stop function release trigger (tkbpahtt0p) = 1 is written while the trigger signal is in its inactive period. 1 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger (tkbpahtt0p) = 1 is written, regardless of the trigger signal level. note 4 1 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writ ing forced output stop function release trigger (tkbpahtt0p) = 1 is invalid. forced output stop function 1 is cleared at the next counter period a fter forced output stop function release trigger (tkbpahtt0p) = 1 is written when the trigger signal is in its inactive period. note 4 tkbpamd0p1 tkbpamd0p0 output status selection when executing forced output stop function forced output stop function 1 forced output stop function 2 0 0 hi-z output output fixed at low level 0 1 hi-z output output fixed at high level 1 0 output fixed at low level output fixed at low level 1 1 output fixed at high level output fixed at high level notes 1. when intp20 is used as the forced output stop function 2, see 14. 5 caution for using timer kb simultaneous operation function . 2. when cmp0 or cmp2 is used as the timer kb forced output stop function, set cmpnsten = 1. see 14. 5 caution for using timer kb simultaneous operation function . 3. when cmp1 is used as the time r kb forced output stop function, see 14. 5 caution for using timer kb simultaneous operation function . 4. when timer kb is stopped (tkbcen = 0) without waiting for the next counter period, the forced output stop function is kept on until timer kb is restarted (tkbcen = 1). cautions 1. during timer operation, setting the other bits of the tkbpactl0p register is prohibited. however, the tkbpactl0p register can be refreshed (the same value is written). 2. be sure to clear bits 11 to 9 and 7 to ?0?. remark n = 0 to 2, p = 0, 1
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 9 of 37 3. figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) incorrect descriptions of forced output st op function control register 1p (tkbpactl1p) are revised, and note is added. incorrect: figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) (1/2) address: f0670h (tkbpactl10), f0672h (tkbpactl11) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 tkbpactl1p tkbpafxs1p3 tkbpafxs1p2 tkbpafxs1p1 tkbpafxs1p0 0 0 0 tkbpafcm1p 7 6 5 4 3 2 1 0 0 tkbpahzs1p2 tkbpahzs1p1 tkbpahzs1p0 tkbpa hcm1p1 tkbpahcm1p0 tkbpamd1p1 tkbpamd1p0 tkbpafxs1p3 external interruption trigger select ion for forced output stop function 2 0 intp20 can not be used as a trigger. 1 intp20 can be used as a trigger. tkbpafxs1p2 comparator trigger selection for forced output stop function 2 0 comparator 3 can not be used as a trigger. 1 comparator 3 can be used as a trigger. tkbpafxs1p1 comparator trigger selection for forced output stop function 2 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. tkbpafxs1p0 comparator trigger selection for forced output stop function 2 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. tkbpafcm1p operation mode selection for forced output stop function 2 0 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period. 1 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger.
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 10 of 37 figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) (2/2) tkbpahzs1p2 comparator trigger selection for forced output stop function 1 0 comparator 3 can not be used as a trigger. 1 comparator 3 can be used as a trigger. tkbpahzs1p1 comparator trigger selection for forced output stop function 1 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. tkbpahzs1p0 comparator trigger selection for forced output stop function 1 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. tkbpahcm1p1 tkbpahcm1p0 clear condition selection for forced output stop function 1 0 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when hi-z stop trigger (tkbpahtt1) = 1 is written, regardless of the trigger signal level. 0 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writing hi-z stop trigger (tkbpahtt1) = 1 is invalid. forced output stop function 1 is cleared when hi-z stop trigger (tkbpahtt1) = 1 is written while the trigger signal is in its inactive period. 1 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared at the next counter period after hi-z stop trigger (tkbpahtt1) = 1 is written, regardless of the trigger signal level. 1 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writing hi-z stop trigger (tkbpahtt1) = 1 is invalid. forced output stop function 1 is cleared at the next counter period after hi-z stop trigger (tkbpahtt1) = 1 is written when the trigger signal is in its inactive period. tkbpamd1p1 tkbpamd1p0 output status selection when executing forced output stop function forced output stop function 1 forced output stop function 2 0 0 hi-z output output fixed at low level 0 1 hi-z output output fixed at high level 1 0 output fixed at low level output fixed at low level 1 1 output fixed at high level output fixed at high level cautions 1. during timer operation, setting the other bits of the tkbpactl1p register is prohibited. however, the tkbpactl1p register can be refreshed (the same value is written). 2. be sure to clear bits 11 to 9 and 7 to ?0?. remark n = 0 to 2, p = 0, 1
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 11 of 37 correct: figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) (1/2) address: f0670h (tkbpactl10), f0672h (tkbpactl11) after reset: 0000h r/w symbol 15 14 13 12 11 10 9 8 tkbpactl1p tkbpafxs1p3 tkbpafxs1p2 tkbpafxs1p1 tkbpafxs1p0 0 0 0 tkbpafcm1p 7 6 5 4 3 2 1 0 0 tkbpahzs1p2 tkbpahzs1p1 tkbpahzs1p0 tkbpa hcm1p1 tkbpahcm1p0 tkbpamd1p1 tkbpamd1p0 tkbpafxs1p3 external interruption trigger select ion for forced output stop function 2 0 intp20 can not be used as a trigger. 1 intp20 can be used as a trigger. note 1 tkbpafxs1p2 comparator trigger selection for forced output stop function 2 0 comparator 3 can not be used as a trigger. 1 comparator 3 can be used as a trigger. note 2 tkbpafxs1p1 comparator trigger selection for forced output stop function 2 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. note 3 tkbpafxs1p0 comparator trigger selection for forced output stop function 2 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. note 3 tkbpafcm1p operation mode selection for forced output stop function 2 0 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period. note 4 1 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger. note 4 tkbpahzs1p2 comparator trigger selection for forced output stop function 1 0 comparator 3 can not be used as a trigger. 1 comparator 3 can be used as a trigger. note 2 tkbpahzs1p1 comparator trigger selection for forced output stop function 1 0 comparator 2 can not be used as a trigger. 1 comparator 2 can be used as a trigger. note 3 tkbpahzs1p0 comparator trigger selection for forced output stop function 1 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. note 3
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 12 of 37 figure 7-74. format of forced output stop function control register 1p (tkbpactl1p) (2/2) tkbpahcm1p1 tkbpahcm1p0 clear condition selection for forced output stop function 1 0 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when forced out put stop function release trigger (tkbpahtt1p) = 1 is written, regard less of the trigger signal level. 0 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writ ing forced output stop function release trigger (tkbpahtt1p) = 1 is invalid. forced output stop function 1 is cleared when forced output stop function release trigger (tkbpahtt1p) = 1 is written while the trigger signal is in its inactive period. 1 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger (tkbpahtt1p) = 1 is written, regardless of the trigger signal level. note 4 1 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writ ing forced output stop function release trigger (tkbpahtt1p) = 1 is invalid. forced output stop function 1 is cleared at the next counter period a fter forced output stop function release trigger (tkbpahtt1p) = 1 is written when the trigger signal is in its inactive period. note 4 tkbpamd1p1 tkbpamd1p0 output status selection when executing forced output stop function forced output stop function 1 forced output stop function 2 0 0 hi-z output output fixed at low level 0 1 hi-z output output fixed at high level 1 0 output fixed at low level output fixed at low level 1 1 output fixed at high level output fixed at high level notes 1. when intp20 is used as the forced output stop function 2, see 14. 5 caution for using timer kb simultaneous operation function . 2. when cmp3 is used as the time r kb forced output stop function, see 14. 5 caution for using timer kb simultaneous operation function . 3. when cmp0 or cmp2 is used as the timer kb forced output stop function, set cmpnsten = 1. for details, see 14. 5 caution for using timer kb simultaneous operation function . 4. when timer kb is stopped (tkbcen = 0) without waiting for the next counter peri od, the forced output stop function is kept on until timer kb is restarted (tkbcen = 1). cautions 1. during timer operation, setting the other bits of the tkbpactl1p register is prohibited. however, the tkbpactl1p register can be refreshed (the same value is written). 2. be sure to clear bits 11 to 9 and 7 to ?0?. remark n = 0 to 2, p = 0, 1
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 13 of 37 4. figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) incorrect descriptions of forced output st op function control register 2p (tkbpactl2p) are revised, and note is added. incorrect: figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) (1/2) address: f06b0h (tkbpactl20) , f06b2h (tkbpactl21) after reset: 0000h r/w gsymbol 15 14 13 12 11 10 9 8 tkbpactl2p tkbpafxs2p3 tkbpafxs2p2 tkbpafxs2p1 tkbpafxs2p0 0 0 0 tkbpafcm2p 7 6 5 4 3 2 1 0 0 tkbpahzs2p2 tkbpahzs2p1 tkbpahzs2p0 tkbpa hcm2p1 tkbpahcm2p0 tkbpamd2p1 tkbpamd2p0 tkbpafxs2p3 external interruption trigger select ion for forced output stop function 2 0 intp20 can not be used as a trigger. 1 intp20 can be used as a trigger. tkbpafxs2p2 comparator trigger selection for forced output stop function 2 0 comparator 5 can not be used as a trigger. 1 comparator 5 can be used as a trigger. tkbpafxs2p1 comparator trigger selection for forced output stop function 2 0 comparator 3 can not be used as a trigger. 1 comparator 3 can be used as a trigger. tkbpafxs2p0 comparator trigger selection for forced output stop function 2 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. tkbpafcm2p operation mode selection for forced output stop function 2 0 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period. 1 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger.
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 14 of 37 figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) (2/2) tkbpahzs2p2 comparator trigger selection for forced output stop function 1 0 comparator 5 can not be used as a trigger. 1 comparator 5 can be used as a trigger. tkbpahzs2p1 comparator trigger selection for forced output stop function 1 0 comparator 4 can not be used as a trigger. 1 comparator 4 can be used as a trigger. tkbpahzs2p0 comparator trigger selection for forced output stop function 1 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. tkbpahcm2p1 tkbpahcm2p0 clear condition selection for forced output stop function 1 0 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when hi-z stop trigger (tkbpahtt2) = 1 is written, regardless of the trigger signal level. 0 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writing hi-z stop trigger (tkbpahtt2) = 1 is invalid. forced output stop function 1 is cleared when hi-z stop trigger (tkbpahtt2) = 1 is written while the trigger signal is in its inactive period. 1 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared at the next counter period after hi-z stop trigger (tkbpahtt2) = 1 is written, regardless of the trigger signal level. 1 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writing hi-z stop trigger (tkbpahtt2) = 1 is invalid. forced output stop function 1 is cleared at the next counter period after hi-z stop trigger (tkbpahtt2) = 1 is written when the trigger signal is in its inactive period. tkbpamd2p1 tkbpamd2p0 output status selection when executing forced output stop function forced output stop function 1 forced output stop function 2 0 0 hi-z output output fixed at low level 0 1 hi-z output output fixed at high level 1 0 output fixed at low level output fixed at low level 1 1 output fixed at high level output fixed at high level cautions 1. during timer operation, setting the other bits of the tkbpactl2p register is prohibited. however, the tkbpactl2p register can be refreshed (the same value is written). 2. be sure to clear bits 11 to 9 and 7 to ?0?. remark n = 0 to 2, p = 0, 1
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 15 of 37 correct: figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) (1/2) address: f06b0h (tkbpactl20) , f06b2h (tkbpactl21) after reset: 0000h r/w gsymbol 15 14 13 12 11 10 9 8 tkbpactl2p tkbpafxs2p3 tkbpafxs2p2 tkbpafxs2p1 tkbpafxs2p0 0 0 0 tkbpafcm2p 7 6 5 4 3 2 1 0 0 tkbpahzs2p2 tkbpahzs2p1 tkbpahzs2p0 tkbpa hcm2p1 tkbpahcm2p0 tkbpamd2p1 tkbpamd2p0 tkbpafxs2p3 external interruption trigger select ion for forced output stop function 2 0 intp20 can not be used as a trigger. 1 intp20 can be used as a trigger. note 1 tkbpafxs2p2 comparator trigger selection for forced output stop function 2 0 comparator 5 can not be used as a trigger. 1 comparator 5 can be used as a trigger. note 2 tkbpafxs2p1 comparator trigger selection for forced output stop function 2 0 comparator 3 can not be used as a trigger. 1 comparator 3 can be used as a trigger. note 2 tkbpafxs2p0 comparator trigger selection for forced output stop function 2 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. note 3 tkbpafcm2p operation mode selection for forced output stop function 2 0 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period. note 4 1 forced output stop function 2 starts with tri gger input, and forced output stop function 2 is cleared at the next counter period following detection of the reverse edge of the trigger. note 4 tkbpahzs2p2 comparator trigger selection for forced output stop function 1 0 comparator 5 can not be used as a trigger. 1 comparator 5 can be used as a trigger. note 2 tkbpahzs2p1 comparator trigger selection for forced output stop function 1 0 comparator 4 can not be used as a trigger. 1 comparator 4 can be used as a trigger. note 2 tkbpahzs2p0 comparator trigger selection for forced output stop function 1 0 comparator 0 can not be used as a trigger. 1 comparator 0 can be used as a trigger. note 3
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 16 of 37 figure 7-75. format of forced output stop function control register 2p (tkbpactl2p) (2/2) tkbpahcm2p1 tkbpahcm2p0 clear condition selection for forced output stop function 1 0 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared when forced out put stop function release trigger (tkbpahtt2p) = 1 is written, regard less of the trigger signal level. 0 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writ ing forced output stop function release trigger (tkbpahtt2p) = 1 is invalid. forced output stop function 1 is cleared when forced output stop function release trigger (tkbpahtt2p) = 1 is written while the trigger signal is in its inactive period. 1 0 forced output stop function 1 starts with trigger input, and forced output stop function 1 is cleared at the next counter period after forced output stop function release trigger (tkbpahtt2p) = 1 is written, regardless of the trigger signal level. note 4 1 1 forced output stop function 1 starts with trigger input, and when the trigger signal is in its active period, writ ing forced output stop function release trigger (tkbpahtt2p) = 1 is invalid. forced output stop function 1 is cleared at the next counter period a fter forced output stop function release trigger (tkbpahtt2p) = 1 is written when the trigger signal is in its inactive period. note 4 tkbpamd2p1 tkbpamd2p0 output status selection when executing forced output stop function forced output stop function 1 forced output stop function 2 0 0 hi-z output output fixed at low level 0 1 hi-z output output fixed at high level 1 0 output fixed at low level output fixed at low level 1 1 output fixed at high level output fixed at high level notes 1. when intp20 is used as the forced output stop function 2, see 14. 5 caution for using timer kb simultaneous operation function . 2. when cmp4 or cmp5 is used as t he timer kb forced output stop function, see 14. 5 caution for using timer kb simultaneous operation function . 3. when cmp0 is used as the timer kb forced output st op function, set cmp0sten = 1. for details, see 14. 5 caution for using timer kb simultaneous operation function . 4. when timer kb is stopped (tkbcen = 0) without waiting for the next counter peri od, the forced output stop function is kept on until timer kb is restarted (tkbcen = 1). cautions 1. during timer operation, setting the other bits of the tkbpactl2p register is prohibited. however, the tkbpactl2p register can be refreshed (the same value is written). 2. be sure to clear bits 11 to 9 and 7 to ?0?. remark n = 0 to 2, p = 0, 1
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 17 of 37 5. figure 14-1. block diagram of comparator incorrect names of the noise filter and the edge detection circuit in the block diagram are revised, and note is added. incorrect: cmpcom/(cmp3p) note / ani18/p147 cmvrs4 cmvrs5 cmvrs6 cmvrs3 cmvrs0 cmvrs2 cmvrs1 comparator internal reference voltage select register m (cmrvm) cmpsel0 comparator input switch control register (cmpsel) wcsel0 wcsel1 wcsel2 window comparator function setting register (cmpwdc) cvre2 cvrvs0 cvrvs1 cvre1 cvre0 comparator internal reference voltage control register (cvrctl) + _ + _ intcmp0 edge detector edge detector edge detector edge detector edge detector edge detector cmp0p/ani2/p22 intp20/p10 intp21/p11 0 1 noise filter noise filter c0oe c0inv c0mod sel0 cmp0en c0dfs1 c0dfs0 c0mod sel1 comparator 0 control register (c0ctl) comparator 0 da0 da1 da2 cegp0 cegn0 comparator rising edge enable register (cmpegp0) comparator falling edge enable register (cmpegn0) cmp0 output timer output forced stop request signal (timers kb0 to kb2) intcmp1, timer restart request signal (timer kb0) timer restart request signal (timers kb0 to kb2) cmp1p/ani4/p24 comparator 1 timer output forced stop request signal (timer kb0) cmpmon0 comparator output monitor register (cmpmon) edge detector 0 1 1 0 1 0 0 1 1 0 external interrupt intp20, intp21 control block cegp6 cegn6 cegp7 cegn7 comparator rising edge enable register (cmpegp0) comparator falling edge enable register (cmpegn1) timer output forced stop request signal (timers kb0 to kb2) timer restart request signal (timers kb0 to kb2) intp20 intp21 edge detector 0 1 timer output forced stop request signal (timers kb0 to kb2) intpinv1intpinv0 external interrupt control register (intpctl) external interrupt edge enable register (egp2, egn2) tmr sten0 tmr sten1 pnfen peripheral function switch register 0 (pfsel0) timer restart request signal (timer kb1) cmp2p/ani5/p25 comparator 2 timer output forced stop request signal (timers kb0, kb1) intcmp3, timer restart request signal (timer kb2) cmp3p/ani6/p26 comparator 3 timer output forced stop request signal (timer kb1) intcmp4 cmp4p/ani7/p27 comparator 4 timer output forced stop request signal (timer kb2) intcmp5 cmp5p/ani16/rxd1/p03 comparator 5 timer output forced stop request signal (timer kb2) v dd av refp /ani0/p20 cvrem bit av refm /ani1/p21 selector v ss wcsel0 bit wcsel2 bit wcsel1 bit da0 da1 da2 + _ + _ + _ + _ note note noise filter cmp0 sten cmp2 sten cmp0sten cmp2sten peripheral function switch register 0 (pfsel0) intcmp2 0 1 selector selector selector selector selector selector selector selector selector selector selector selector edge detector note 20-pin products only. ani16/cmp3p/p26 is selected by default for 30- and 38-pin products. remark m = 0 to 2
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 18 of 37 correct: cmpcom/(cmp3p) note / ani18/p147 cmvrs4 cmvrs5 cmvrs6 cmvrs3 cmvrs0 cmvrs2 cmvrs1 comparator internal reference voltage select register m (cmrvm) cmpsel0 comparator input switch control register (cmpsel) wcsel0 wcsel1 wcsel2 window comparator function setting register (cmpwdc) cvre2 cvrvs0 cvrvs1 cvre1 cvre0 comparator internal reference voltage control register (cvrctl) + _ + _ intcmp0 digital edge detector cmp0p/ani2/p22 intp20/p10 intp21/p11 0 1 digital noise filter noise filter c0oe c0inv c0mod sel0 cmp0en c0dfs1 c0dfs0 c0mod sel1 comparator 0 control register (c0ctl) comparator 0 da0 da1 da2 cegp0 cegn0 comparator rising edge enable register (cmpegp0) comparator falling edge enable register (cmpegn0) cmp0 output timer output forced stop request signal (timers kb0 to kb2) intcmp1, timer restart request signal (timer kb0) timer restart request signal (timers kb0 to kb2) cmp1p/ani4/p24 comparator 1 timer output forced stop request signal (timer kb0) cmpmon0 comparator output monitor register (cmpmon) 0 1 1 0 1 0 0 1 1 0 external interrupt intp20, intp21 control block cegp6 cegn6 cegp7 cegn7 comparator rising edge enable register (cmpegp0) comparator falling edge enable register (cmpegn1) timer output forced stop request signal (timers kb0 to kb2) timer restart request signal (timers kb0 to kb2) intp20 intp21 0 1 timer output forced stop request signal (timers kb0 to kb2) intpinv1intpinv0 external interrupt control register (intpctl) external interrupt edge enable register (egp2, egn2) tmr sten0 tmr sten1 pnfen peripheral function switch register 0 (pfsel0) timer restart request signal (timer kb1) cmp2p/ani5/p25 comparator 2 timer output forced stop request signal (timers kb0, kb1) intcmp3, timer restart request signal (timer kb2) cmp3p/ani6/p26 comparator 3 timer output forced stop request signal (timer kb1) intcmp4 cmp4p/ani7/p27 comparator 4 timer output forced stop request signal (timer kb2) intcmp5 cmp5p/ani16/rxd1/p03 comparator 5 timer output forced stop request signal (timer kb2) v dd av refp /ani0/p20 cvrem bit av refm /ani1/p21 selector v ss wcsel0 bit wcsel2 bit wcsel1 bit da0 da1 da2 + _ + _ + _ + _ note note noise filter cmp0 sten cmp2 sten cmp0sten cmp2sten peripheral function switch register 0 (pfsel0) intcmp2 0 1 selector selector selector selector selector selector selector selector selector selector selector selector edge detector digital edge detector digital edge detector digital edge detector digital edge detector digital edge detector digital edge detector digital edge detector note 20-pin products only. ani16/cmp3p/p26 is selected by default for 30- and 38-pin products. caution when intp20, intp21, and comparator are used as the timer kb forced output stop function 2 or timer kb restart function, see 14. 5 caution for us ing timer kb simultaneous operation function. remark m = 0 to 2
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 19 of 37 6. figure 14-12. format of peripheral function switch register 0 (pfsel0) incorrect descriptions of the comparator and ex ternal interrupts are revised, and notes are added. incorrect: figure 14-12. format of peripheral function switch register 0 (pfsel0) address: f05c6h after reset: 00h r/w symbol 7 <6> <5> <4> 3 2 <1> <0> pfsel0 0 cmp2sten cmp0sten pnfen adtrg11 adtrg10 tmrsten1 tmrsten0 cmp2sten comparator 2 detection interrupt (intcmp2) switching 0 stop mode clear disabled 1 stop mode clear enabled, but only when not using noise filter (can be set when operating in low-power rtc mode (rtclpc = 1 in the osmc register) cmp0sten comparator 0 detection interrupt (intcmp0) switching 0 stop mode clear disabled 1 stop mode clear enabled, but only when not using noise filter (can be set when operating in low-power rtc mode (rtclpc = 1 in the osmc register) pnfen use/do not use external interrupt intp20 noise filter 0 use noise filter 1 do not use noise filter tmrsten1 external interrupt intp21 function select 0 external interrupt function (can be generated ex ternal interrupt, but cannot be used for timer restart function) 1 timer restart function (cannot be generated ex ternal interrupt, and cannot release standby mode) tmrsten0 external interrupt intp20 function select 0 external interrupt function (can be generated ex ternal interrupt, but cannot be used for timer restart function) 1 timer restart function (cannot be generated ex ternal interrupt, and cannot release standby mode) caution comparator detection interrupt other than cmp0 and cmp2 cannot be used to clear the stop mode.
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 20 of 37 correct: figure 14-12. format of peripheral function switch register 0 (pfsel0) address: f05c6h after reset: 00h r/w symbol 7 <6> <5> <4> 3 2 <1> <0> pfsel0 0 cmp2sten cmp0sten pnfen adtrg11 adtrg10 tmrsten1 tmrsten0 cmp2sten comparator 2 detection interrupt (intcmp2) switching note 1 0 signal via digital edge detect circuit is sele cted. stop mode release is disabled. 1 forced output stop request signal is selected. stop mode release is enabled, but only when not using noise filter. (can be set when operating in low-power rtc mode (rtclpc = 1 in the osmc register) cmp0sten comparator 0 detection interrupt (intcmp0) switching note 1 0 signal via digital edge detect circuit is sele cted. stop mode release is disabled. 1 forced output stop request signal is selected. stop mode release is enabled, but only when not using noise filter. (can be set when operating in low-power rtc mode (rtclpc = 1 in the osmc register) pnfen use/do not use external interrupt intp20 noise filter 0 use noise filter 1 do not use noise filter tmrsten1 external interrupt intp21 function switching note 2 0 external interrupt function is selected. (s top mode release is enabled, but cannot be used for timer restart function) 1 timer restart function is selected. (stop mode release is disabled, but can be used for timer restart function) tmrsten0 external interrupt intp20 function switching note 2 0 external interrupt function is selected. (s top mode release is enabled, but cannot be used for timer restart function) 1 timer restart function/forced output stop functi on 2 is selected. (stop mode release is disabled, but can be used fo r timer restart function) notes 1. when the interrupt for cmp0 and cmp2 is used, adopt a function used with the interrupt input signal. when the cmp0 and cmp2 are used as a trigger of the timer kb forced out put stop function, set cmpnsten = 1. when the cmp2 is used as a trigger of the timer re start function for timer kb, set cmp2sten = 0. for details, see 14. 5 caution for using timer kb simultaneous operation function . 2. when intp20 and intp21 are used as a trigger of the timer kb forced output stop function 2 or timer restart function, see 14. 5 caution for using timer kb simultaneous operation function . caution comparator detection interrupt other than cmp0 and cmp2 cannot be used to clear the stop mode. remark n = 0, 2
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 21 of 37 7. 14. 5 caution for using timer kb simultaneous operation function as respects of intp2m and comparator, caution for us ing timer kb simultaneous operation function is added. incorrect: no applicable item correct: 14. 5 caution for using timer kb simultaneous operation function in addition to their use as an external interrupt input, the in tp2m pin output and the comparat or output signal can be used as a trigger for functions that operate simultaneously with time r kb, such as the forced output stop function and timer restart function. the settings in peripheral function switch register 0 (pfsel0) and the edge selectio n registers must be specified according to the function used. the width of the active signal required until each function starts operating differs. when using intp2m or the comparator output signal, refer to t ables 14-4 to 14-6 to specify the necessary register settings, and configure external circuits so that t he required active signal width is assured. table 14-4. relationship of intp2m function, register settings, and active signal width function peripheral enable register setting edge setting registers necessary active signal width to operate each function interrupt forced output stop timer restart external interrupt (stop release is enabled) tmrstenm = 0 egpn, egnn to 1 ? s - - forced output stop note 1 tmrstenm = 1 cegpp, cegnp note 2 55 to 215 ns note 3 + 2 to 3 clocks note 4 55 to 215 ns note 3, 5 - timer restart tmrstenm = 1 cegpp, cegnp 55 to 215 ns note 3 + 2 to 3 clocks note 4 - 55 to 215 ns note 3 + 2 to 3 clocks note 4, 6 figure 14-18. generation timing of forced output stop signal and timer restart request signal by intp2m intp2m pin timer restart request signal, interrupt request signal forced output stop request signal note 1 internal wait time (55 to 215 ns ) note 3, 5 edge comfirming time (2 to 3 clocks ) note 4, 6 notes 1. only intp20 can be used as a trigger for forced output stop function 2. 2. the active level of intp20 (used for forced output stop f unction 2) is high. edge selection is only applied to detection of an interrupt signal. 3. 5 to 15 ns when noise filtering on intp20 is disabled (pnfen = 1) 4. for f clk or f pll (when pllon = 1) 5. an additional output delay time (10 to 40 ns) is r equired from when forced outpu t stop function 2 starts operating to when the level of the timer kb output changes.
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 22 of 37 notes 6. until the timer restart function st arts operating, an additional clock cycl e is required after the timer restart request signal is received, and an additional output delay time (10 to 40 ns) is required until the level of the timer kb output changes. remark m = 0, 1 n = 20, 21 p = 7, 6 table 14-5. relationship of comparator 0 and 2 func tions, register settings, and active signal width function peripheral enable register setting edge setting registers necessary active signal width to operate each function interrupt forced output stop timer restart external interrupt (stop release is enabled note 1 ) cmpnsten = 1 rising edge only note 2 to 150 ns note 3 - - external interrupt (stop release is disabled) cmpnsten = 0 cegpn, cegnn to 150 ns note 3 + 2 to 3 clocks note 4, 5 - - forced output stop cmpnsten = 1 note 6 to 150 ns note 3 to 150 ns note 3, 7 - timer restart cmpnsten = 0 cegpn, cegnn to 150 ns note 3 + 2 to 3 clocks note 4, 5 - to 150 ns note 3 + 2 to 3 clocks note 4, 5 figure 14-19. generation timing of forced output stop request signal by comparator 0 and 2 (cmpnsten = 1) cmpnp pin comparator respondence time (to 150 ns ) note 3 interrupt request signal forced output stop request signal, figure 14-20. generation timing of timer restart request signal by comparator 0 and 2 (cmpnsten = 0) cmpnp pin timer restart request signal, interrupt request signal comparator output signal comparator respondence time (to 150 ns ) note 3 edge comfirming time (2 to 3 clocks ) note 4, 5 notes 1. when noise filtering is set to "0, 0" by using the cndfs1 and cndfs0 bits in the comparator n control register (cnctl) 2. to change the level of the edge directi on, invert the comparator output si gnal by using the cninv bit in the comparator n control register (cnctl). 3. this is the time required when noise filtering is set to "0, 0" by using the cndfs1 and cndfs0 bits in the comparator n control register (cnctl). if a setting other than "0, 0" is specified, t he specified noise elimin ation width is added. 4. for f clk or f pll (when pllon = 1)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 23 of 37 notes 5. until the timer restart function st arts operating, an additional clock cycl e is required after the timer restart request signal is received, and an additional output delay time (10 to 40 ns) is required until the level of the timer kb output changes. 6. the active level of intp20 (used for forced output stop function 2) is high. 7. an additional output delay time (10 to 40 ns) is r equired from when forced outpu t stop function 2 starts operating to when the level of the timer kb output changes. remark n = 0, 2 table 14-6. relationship of comparator 1, 3, 4, and 5 functions, register settings, and active signal width function peripheral enable register setting edge setting registers necessary active signal width to operate each function interrupt forced output stop timer restart external interrupt (stop release is disabled) - cegpn, cegnn to 150 ns note 1 + 2 to 3 clocks note 2, 3 - - forced output stop - note 4 to 150 ns note 2 + 2 to 3 clocks note 3, 4 to 150 ns note 2, 5 - timer restart note 6 - cegpn, cegnn to 150 ns note 2 + 2 to 3 clocks note 3, 4 - to 150 ns note 2 + 2 to 3 clocks note 3, 4 figure 14-21. generation timing of forced output stop request signal and timer restart request signal by comparator 1, 3, 4, and 5 timer restart request signal , interrupt request signal forced output stop request signal edge comfirming time (2 to 3 clocks ) note 2, 3 comparator respondence time (to 150 ns ) note 1 cmpnp pin note 5 notes 1. when noise filtering is set to "0, 0" by using the cndfs1 and cndfs0 bits in the comparator n control register (cnctl). if a setting other than "0, 0" is specifi ed, the specified noise e limination width is added. 2. for f clk or f pll (when pllon = 1) 3. until the timer restart function st arts operating, an additional clock cycl e is required after the timer restart request signal is received, and an additional output delay time (10 to 40 ns) is required until the level of the timer kb output changes. 4. the active level of intp20 (used for forced output stop function 2) is high. 5. an additional output delay time (10 to 40 ns) is r equired from when forced outpu t stop function 2 starts operating to when the level of the timer kb output changes. 6. the timer restart function can be used for comparator 1 and 3 only . 7. an additional output delay time (10 to 40 ns) is r equired from when forced outpu t stop function 2 starts operating to when the level of the timer kb output changes. remark n = 1, 3 to 5
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 24 of 37 8. timing chart of snooze mode operation (p.666, 667, 669) incorrect the clock request signal (internal signal) timing is revised. incorrect: figure 15-90. timing chart of snooze m ode operation (eocm1 = 0, ssecm = 0/1) ss01 se01 swc0 ssec0 l eoc01 l sdr01 intsr0 intsre0 l tsf01 <1> <2> <3> <5><6> <8> <7> <9> <4> st01 rxd0 pin p st p sp sp st <10> <11> <12> cpu operation status normal operation stop mode snooze mode normal operation receive data 1 receive data 2 receive data 2 receive data 1 shift operation shift operation data reception data reception shift register 01 clock request signal (internal signal) read note correct: figure 15-90. timing chart of snooze m ode operation (eocm1 = 0, ssecm = 0/1) ss01 se01 swc0 ssec0 l eoc01 l sdr01 intsr0 intsre0 l tsf01 <1> <2> <3> <5> <6> <8> <7> <9> <4> st01 rxd0 pin p st p sp sp st <10> <11> <12> cpu operation status normal operation stop mode snooze mode normal operation receive data 1 receive data 2 receive data 2 receive data 1 shift operation shift operation data reception data reception shift register 01 clock request signal (internal signal) read note
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 25 of 37 incorrect the timing chart of clock request signal (internal signal) and sdr01 is revised. incorrect: figure 15-91. timing chart of snooze m ode operation (eocm1 = 1, ssecm = 0) ss01 se01 swc0 ssec0 l sdr01 intsr0 intsre0 l tsf01 <1> <2> <3> <5> <6> <8> <7> <3> <4> st01 rxd0 pin p st p sp sp st <10> <11> <12> cpu operation status normal operation stop mode snooze mode normal operation clock request signal (internal signal) shift register 01 receive data 1 receive data 1 receive data 2 receive data 2 shift operation shift operation data reception data reception eoc01 correct: figure 15-91. timing chart of snooze m ode operation (eocm1 = 1, ssecm = 0) ss01 se01 swc0 ssec0 l sdr01 intsr0 intsre0 l tsf01 <1> <2> <3> <5> <6> <8> <7> <4> st01 rxd0 pin p st p sp sp st <10> <11> <12> cpu operation status normal operation stop mode snooze mode normal operation clock request signal (internal signal) shift register 01 receive data 1 receive data 1 receive data 2 receive data 2 shift operation shift operation data reception data reception eoc01 <9> read note
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 26 of 37 incorrect the clock request signal (int ernal signal) timing chart is revised. incorrect: figure 15-93. timing chart of snooze m ode operation (eocm1 = 1, ssecm = 1) l <1> <2> <3> <5> <6> <7> <6> <9> <4> p p sp sp st <7>, <8> <5> st ss01 se01 swc0 ssec0 sdr01 intsr0 intsre0 tsf01 st01 rxd0 pin <10> <11> cpu operation status normal operation stop mode snooze mode stop mode snooze mode normal operation receive data 1 receive data 2 receive data 2 receive data 1 shift operation shift operation data reception data reception shift register 01 clock request signal (internal signal) read note 1 eoc01 correct: figure 15-93. timing chart of snooze m ode operation (eocm1 = 1, ssecm = 1) l <1> <2> <3> <5> <6> <7> <6> <9> <4> p p sp sp st <7>, <8> <5> st ss01 se01 swc0 ssec0 sdr01 intsr0 intsre0 tsf01 st01 rxd0 pin <10> <11> cpu operation status normal operation stop mode snooze mode stop mode snooze mode normal operation receive data 1 receive data 2 receive data 2 receive data 1 shift operation shift operation data reception data reception shift register 01 clock request signal (internal signal) read note 1 eoc01
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 27 of 37 9. table 20-1. interrupt source list (2/3) note for the interrupt source list is added. incorrect: notes 1. the default priority determines the sequence of inte rrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 40 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 20-1. 3. intcmp1, intcmp3, intcmp4, and intcmp5 cannot be used to clear the stop mode. correct: notes 1. the default priority determines the sequence of inte rrupts if two or more maskable interrupts occur simultaneously. zero indicates the highest priority and 40 indicates the lowest priority. 2. basic configuration types (a) to (d) co rrespond to (a) to (d) in figure 20-1. 3. intcmp1, intcmp3, intcmp4, and intcmp5 cannot be used to clear the stop mode. about interrupt generation timing, see 14. 5 caution for using timer kb simultaneous operation function .
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 28 of 37 10. figure 20-1. basic configuration of interrupt function incorrect the basic configuration of interrupt function is revised. incorrect: (b) external maskable in terrupt (intpn, intcmpm) if mk ie pr1 isp1 pr0 isp0 internal bus external interrupt edge enable register (egp, egn) intpn, intcmpm pin input edge detector priority controller vector table address generator standby release signal if: interrupt request flag ie: interrupt enable flag isp0: in-service priority flag 0 isp1: in-service priority flag 1 mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 remark 20-pin: n = 0, 20, 21, 22, m = 0 to 3 30-pin: n = 0, 4, 11, 20 to 23, m = 0 to 5 38-pin: n = 0, 3, 4, 9 to 11, 20 to 23, m = 0 to 5
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 29 of 37 correct: (b) external maskable in terrupt (intpn, intcmpm) if mk ie pr1 isp1 pr0 isp0 internal bus external interrupt edge enable register (egp, egn) edge detector priority controller vector table address generator standby release signal note note intpn , intcmpm pin input note note note according to setting for using of the timer kb simultane ous function (the timer kb forc ed output stop function and timer restart function), the interrupt signal pass and the in terrupt generation timing and the edge enable register for intp20 and intp21 and intcmpm vary. for details, see 14. 5 caution for using timer kb simultaneous operation function . if: interrupt request flag ie: interrupt enable flag isp0: in-service priority flag 0 isp1: in-service priority flag 1 mk: interrupt mask flag pr0: priority specification flag 0 pr1: priority specification flag 1 remark 20-pin: n = 0, 20, 21, 22, m = 0 to 3 30-pin: n = 0, 4, 11, 20 to 23, m = 0 to 5 38-pin: n = 0, 3, 4, 9 to 11, 20 to 23, m = 0 to 5
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 30 of 37 11. table 21-1. operating statuses in halt mode (2/2) incorrect description about the comparator operation in halt mode is revised. incorrect: halt mode setting item when halt instruction is executed while cpu is operating on subsystem clock when cpu is operating on xt1 clock (f xt ) when cpu is operating on external subsystem clock (f exs ) system clock clock supply to the cpu is stopped main system clock f ih operation disabled f x f ex subsystem clock f xt operation continues (cannot be stopped) cannot operate f exs cannot operate operation continues (cannot be stopped) f il set by bits 0 (wdstbyon) and 4 (wdton) of option byte (000c0h), and wutmmck0 bit of operation speed mode control register (osmc) ? wutmmck0 = 1: oscillates ? wutmmck0 = 0 and wdton = 0: stops ? wutmmck0 = 0, wdton = 1, and wdstbyon = 1: oscillates ? wutmmck0 = 0, wdton = 1, and wdstbyon = 0: stops cpu operation stopped code flash memory data flash memory ram port (latch) status before halt mode was set is retained timer array unit operable when the rtclpc bit is 0 ( operation is disabled when the rtclpc bit is not 0). timer kb0 to kb2 timer kc0 real-time clock (rtc) operable 12-bit interval timer watchdog timer see chapter 11 watchdog timer a/d converter operation disabled programmable gain amplifier operable (however, this is not used, since the operation has been disabled for the a/d converter that is the destination for input of the pga output signal) comparator operable (when in the low-consumption rtc mode (rtclpc = 1 in the osmc register), this can be used only when the stop m ode cancel is set (cmpnsten = 1 in the pfsel0 register) by the comparator interrupt detection and the noise filter is not used (n = 0, 2)) (omitted)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 31 of 37 correct: halt mode setting item when halt instruction is executed while cpu is operating on subsystem clock when cpu is operating on xt1 clock (f xt ) when cpu is operating on external subsystem clock (f exs ) system clock clock supply to the cpu is stopped main system clock f ih operation disabled f x f ex subsystem clock f xt operation continues (cannot be stopped) cannot operate f exs cannot operate operation continues (cannot be stopped) f il set by bits 0 (wdstbyon) and 4 (wdton) of option byte (000c0h), and wutmmck0 bit of operation speed mode control register (osmc) ? wutmmck0 = 1: oscillates ? wutmmck0 = 0 and wdton = 0: stops ? wutmmck0 = 0, wdton = 1, and wdstbyon = 1: oscillates ? wutmmck0 = 0, wdton = 1, and wdstbyon = 0: stops cpu operation stopped code flash memory data flash memory ram port (latch) status before halt mode was set is retained timer array unit operable when the rtclpc bit is 0 ( operation is disabled when the rtclpc bit is not 0). timer kb0 to kb2 timer kc0 real-time clock (rtc) operable 12-bit interval timer watchdog timer see chapter 11 watchdog timer a/d converter operation disabled programmable gain amplifier operable (however, this is not used, since the operation has been disabled for the a/d converter that is the destination for input of the pga output signal) comparator only cmp0 and cmp2 are operable. (when in the low-consumption rtc mode (rtclpc = 1 in the osmc register), cmpn can be us ed only when the stop mode cancel is set (cmpnsten = 1 in the pfsel0 register) by the comparator interrupt detection and the noise filter is not used. (n = 0, 2)) (omitted)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 32 of 37 12. table 21-2. operating statuses in stop mode incorrect description about the comparator operation in stop mode is revised. incorrect: stop mode setting item when stop instruction is executed while cpu is operating on main system clock when cpu is operating on high-speed on-chip oscillator clock (f ih ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped main system clock f ih stopped f x f ex subsystem clock f xt status before stop mode was set is retained f exs f il set by bits 0 (wdstbyon) and 4 (wdton) of option byte (000c0h), and wutmmck0 bit of operation speed mode control register (osmc) ? wutmmck0 = 1: oscillates ? wutmmck0 = 0 and wdton = 0: stops ? wutmmck0 = 0, wdton = 1, and wdstbyon = 1: oscillates ? wutmmck0 = 0, wdton = 1, and wdstbyon = 0: stops cpu operation stopped code flash memory data flash memory ram port (latch) status before stop mode was set is retained timer array unit operation disabled timer kb0 to kb2 timer kc0 real-time clock (rtc) operable 12-bit interval timer watchdog timer see chapter 11 watchdog timer a/d converter wakeup operation is enabl ed (switching to the snooze mode) programmable gain amplifier operable comparator operable (only for channels set to enable canc ellation of stop mode and when digital filter is not used) (omitted)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 33 of 37 correct: stop mode setting item when stop instruction is executed while cpu is operating on main system clock when cpu is operating on high-speed on-chip oscillator clock (f ih ) when cpu is operating on x1 clock (f x ) when cpu is operating on external main system clock (f ex ) system clock clock supply to the cpu is stopped main system clock f ih stopped f x f ex subsystem clock f xt status before stop mode was set is retained f exs f il set by bits 0 (wdstbyon) and 4 (wdton) of option byte (000c0h), and wutmmck0 bit of operation speed mode control register (osmc) ? wutmmck0 = 1: oscillates ? wutmmck0 = 0 and wdton = 0: stops ? wutmmck0 = 0, wdton = 1, and wdstbyon = 1: oscillates ? wutmmck0 = 0, wdton = 1, and wdstbyon = 0: stops cpu operation stopped code flash memory data flash memory ram port (latch) status before stop mode was set is retained timer array unit operation disabled timer kb0 to kb2 timer kc0 real-time clock (rtc) operable 12-bit interval timer watchdog timer see chapter 11 watchdog timer a/d converter wakeup operation is enabl ed (switching to the snooze mode) programmable gain amplifier operable comparator only cmp0 and cmp2 are operable when the stop mode cancel is set (cmpnsten = 1 in the pfsel0 register) by the comparator interrupt detection and the noise filter is not used. (n = 0, 2) (omitted)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 34 of 37 13. table 21-3. operating statuses in snooze mode incorrect description about the comparator operation in snooze mode is revised. incorrect: stop mode setting item when inputting csi00/uart0 data reception si gnal or a/d converter timer trigger signal while in stop mode when cpu is operating on high-speed on-chip oscillator clock (f ih ) system clock clock supply to the cpu is stopped main system clock f ih operation started f x stopped f ex subsystem clock f xt use of the status while in the stop mode continues f exs f il set by bits 0 (wdstbyon) and 4 (wdton) of option byte (000c0h), and wutmmck0 bit of operation speed mode control register (osmc) ? wutmmck0 = 1: oscillates ? wutmmck0 = 0 and wdton = 0: stops ? wutmmck0 = 0, wdton = 1, and wdstbyon = 1: oscillates ? wutmmck0 = 0, wdton = 1, and wdstbyon = 0: stops cpu operation stopped code flash memory data flash memory ram port (latch) use of the status while in the stop mode continues timer array unit operation disabled timer kb0 to kb2 timer kc0 real-time clock (rtc) operable 12-bit interval timer watchdog timer see chapter 11 watchdog timer a/d converter operable programmable gain amplifier operable comparator operable (only for channels set to enable cancellation of stop m ode and when digital filter is not used) (omitted)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 35 of 37 correct: stop mode setting item when inputting csi00/uart0 data reception si gnal or a/d converter timer trigger signal while in stop mode when cpu is operating on high-speed on-chip oscillator clock (f ih ) system clock clock supply to the cpu is stopped main system clock f ih operation started f x stopped f ex subsystem clock f xt use of the status while in the stop mode continues f exs f il set by bits 0 (wdstbyon) and 4 (wdton) of option byte (000c0h), and wutmmck0 bit of operation speed mode control register (osmc) ? wutmmck0 = 1: oscillates ? wutmmck0 = 0 and wdton = 0: stops ? wutmmck0 = 0, wdton = 1, and wdstbyon = 1: oscillates ? wutmmck0 = 0, wdton = 1, and wdstbyon = 0: stops cpu operation stopped code flash memory data flash memory ram port (latch) use of the status while in the stop mode continues timer array unit operation disabled timer kb0 to kb2 timer kc0 real-time clock (rtc) operable 12-bit interval timer watchdog timer see chapter 11 watchdog timer a/d converter operable programmable gain amplifier operable comparator only cmp0 and cmp2 are operable when the stop mode cancel is set (cmpnsten = 1 in the pfsel0 register) by the comparator interrupt detection and the noise filter is not used. (n = 0, 2) (omitted)
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 36 of 37 14. 32.7 data memory stop mode low supply voltage data retention characteristics descriptions of the data memory stop mode low suppl y voltage data retention char acteristics are added. incorrect: 32.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +105 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the por detection voltage. when the voltage drops, the data is retained before a por reset is effected, but data is not retain ed when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode correct: 32.7 ram data retention characteristics (t a = ? 40 to +105 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.44 note 5.5 v note the value depends on the por detection voltage. when t he voltage drops, the ram data is retained before a por reset is effected, but ram data is not re tained when a por reset is effected. caution when cpu is operated at the voltage of out of the operation voltage range, ram data is not retained. therefore, set stop mode before the supplied voltage is below the operation voltage range. v dd stop instruction execution standby release signal (interrupt request) stop mode ram data retention v dddr operation mode
renesas technical update tn-rl*-a024a/e date: apr. 9, 2014 page 37 of 37 15. 33.7 data memory stop mode low supply voltage data retention characteristics descriptions of the data memory stop mode low suppl y voltage data retention char acteristics are added. incorrect: 33.7 data memory stop mode low supply voltage data retention characteristics (t a = ? 40 to +125 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.47 note 5.5 v note the value depends on the por detection voltage. when the voltage drops, the data is retained before a por reset is effected, but data is not retain ed when a por reset is effected. v dd stop instruction execution standby release signal (interrupt request) stop mode data retention mode v dddr operation mode correct: 33.7 ram data retention characteristics (t a = ? 40 to +125 ? c, v ss = 0 v) parameter symbol conditions min. typ. max. unit data retention supply voltage v dddr 1.47 note 5.5 v note the value depends on the por detection voltage. when t he voltage drops, the ram data is retained before a por reset is effected, but ram data is not re tained when a por reset is effected. caution when cpu is operated at the voltage of out of the operation voltage range, ram data is not retained. therefore, set stop mode before the supplied voltage is below the operation voltage range. v dd stop instruction execution standby release signal (interrupt request) stop mode ram data retention v dddr operation mode

▲Up To Search▲

Price & Availability of TNRLA024AE

	To Download TNRLA024AE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .